Computer architecture · Beijing

Xia Zhao 赵夏

Selected for National Youth Talent Plan

Associate Researcher in computer architecture

Academy of Military Science
Artificial Intelligence Research Center

Selected work Research focus
Portrait of Xia Zhao outdoors
Focus
GPU & CPU microarchitecture
Systems
Chiplets, memory & interconnects
Office
Beijing, China

About

Building efficient computing systems.

My work explores how processors, memory systems, and on-chip networks can be redesigned together for emerging workloads.

I received my B.S. from the School of Computer Science & Technology at Huazhong University of Science & Technology in 2012, and my M.S. from the College of Computer at the National University of Defense Technology in 2014.

I completed my Ph.D. at Ghent University in 2019 under the supervision of Professor Lieven Eeckhout. I am currently an Associate Researcher. My research interests span computer architecture, with particular emphasis on GPU and CPU microarchitecture. Alongside my research, I lead a large processor-design team developing high-performance CPUs tailored to AI-agent workloads.

Research

Current directions

I focus on architecture mechanisms that improve performance and efficiency without losing sight of implementation cost.

01

GPU architectures

Microarchitectural techniques for resource utilization, workload diversity, multitasking, and irregular memory behavior.

02

Chiplets & memory systems

Cache, interconnect, and data-placement designs for many-chip-module processors and bandwidth-constrained systems.

03

CPU microarchitecture

High-performance processor cores, memory hierarchies, and architecture support for emerging intelligent workloads.

Engineering

From architecture ideas to working CPUs.

I lead a large processor-design team building high-performance CPUs for AI-agent workloads, spanning microarchitecture, RTL implementation, verification, and prototype-system validation.

Cartoon illustration of a modern multicore CPU die
01

High-performance branch prediction

We design scalable prediction structures and front-end mechanisms that sustain instruction delivery under complex control flow.

02

Latency-optimized memory hierarchy

We optimize cache and TLB pipelines, prefetching, and miss-handling paths to reduce load-to-use latency and long-tail stalls.

03

CPU implementation & integration

We build out-of-order cores from the front end through execution and memory, balancing frequency, performance, power, and implementation complexity.

04

CPU verification platform

We develop reusable simulation, random-instruction generation, differential testing, coverage, and full-system regression infrastructure.

Publications

Recent publications

Recent conference and journal work on GPU organization, many-chip-module systems, memory hierarchies, and on-chip communication.

  1. 2025
    UGPU: Dynamically Constructing Unbalanced GPUs for Enhanced Resource Efficiency

    Xia Zhao, Guangda Zhang, Lu Wang, and Huadong Dai

    ISCA
  2. 2025
    NearFetch: Saving Inter-Module Bandwidth in Many-Chip-Module GPUs

    Xia Zhao, Guangda Zhang, Lu Wang, Shiqing Zhang, and Huadong Dai

    HPCA
  3. 2024
    ChameSC: Virtualizing Superscalar Core of a SIMD Architecture for Vector Memory Accesses

    Zhongzhu Pu, Guangda Zhang, Tiejian Zhang, Chen Zhang, Youhui Zhang, and Xia Zhao

    ICCD
  4. 2024
    AdCoalescer: An Adaptive Coalescer to Reduce the Inter-Module Traffic in MCM-GPUs

    Xu Zhang, Guangda Zhang, Lu Wang, Shiqing Zhang, and Xia Zhao

    ICPP
  5. 2023
    NUBA: Non-Uniform Bandwidth GPUs

    Xia Zhao, Magnus Jahre, Yuhua Tang, Guangda Zhang, and Lieven Eeckhout

    ASPLOS
  6. 2023
    RouteReplies: Alleviating Long Latency in Many-Chip-Module GPUs

    Xia Zhao, Guangda Zhang, Lu Wang, Yangmei Li, and Yongjun Zhang

    IEEE CAL · Journal
  7. 2022
    Delegated Replies: Alleviating Network Clogging in Heterogeneous Architectures

    Xia Zhao, Lieven Eeckhout, and Magnus Jahre

    HPCA
Earlier conference and journal publications

Conference publications

  1. 2020Selective Replication in Memory-Side GPU Caches. Xia Zhao, Magnus Jahre, and Lieven Eeckhout. MICRO.
  2. 2020HSM: A Hybrid Slowdown Model for Multitasking GPUs. Xia Zhao, Magnus Jahre, and Lieven Eeckhout. ASPLOS.
  3. 2019Adaptive Memory-Side Last-Level GPU Caching. Xia Zhao, Almutaz Adileh, Zhibin Yu, Zhiying Wang, Aamer Jaleel, and Lieven Eeckhout. ISCA.
  4. 2018Classification-Driven Search for Effective SM Partitioning in GPU Multitasking. Xia Zhao, Zhiying Wang, and Lieven Eeckhout. ICS.
  5. 2018Get Out of the Valley: Power-Efficient Address Mapping for GPUs. Yuxi Liu, Xia Zhao, Magnus Jahre, Zhenlin Wang, Xiaolin Wang, Yingwei Luo, and Lieven Eeckhout. ISCA.
  6. 2018Intra-Cluster Coalescing to Reduce GPU NoC Pressure. Lu Wang, Xia Zhao, David Kaeli, Zhiying Wang, and Lieven Eeckhout. IPDPS.
  7. 2017BACM: Barrier-Aware Cache Management for Irregular Memory-Intensive GPGPU Workloads. Yuxi Liu, Xia Zhao, Zhibin Yu, Zhenlin Wang, Xiaolin Wang, Yingwei Luo, and Lieven Eeckhout. ICCD.
  8. 2017BACM: Barrier-Aware Cache Management for Irregular Memory-Intensive GPGPU Workloads. Yuxi Liu, Xia Zhao, Zhibin Yu, Zhenlin Wang, Xiaolin Wang, Yingwei Luo, and Lieven Eeckhout. PACT Poster.
  9. 2016A Low-Cost Conflict-Free NoC for GPGPUs. Xia Zhao, Sheng Ma, Yuxi Liu, Lieven Eeckhout, and Zhiying Wang. DAC.
  10. 2016A Heterogeneous Low-Cost and Low-Latency Ring-Chain Network for GPGPUs. Xia Zhao, Sheng Ma, Chen Li, Lieven Eeckhout, and Zhiying Wang. ICCD.

Journal publications

  1. 2019CD-Xbar: A Converge-Diverge Crossbar Network for High-Performance GPUs. Xia Zhao, Sheng Ma, Zhiying Wang, Natalie Enright Jerger, and Lieven Eeckhout. IEEE Transactions on Computers. Featured Paper.
  2. 2019Intra-Cluster Coalescing to Reduce GPU NoC Pressure. Lu Wang, Xia Zhao, David Kaeli, Zhiying Wang, and Lieven Eeckhout. IEEE Transactions on Computers.
  3. 2018HeteroCore GPU to Exploit TLP-Resource Diversity. Xia Zhao, Zhiying Wang, and Lieven Eeckhout. IEEE Transactions on Parallel and Distributed Systems.
  4. 2017LA-LLC: Inter-Core Locality-Aware Last-Level Cache to Exploit Many-to-Many Traffic in GPGPUs. Xia Zhao, Yuxi Liu, Almutaz Adileh, and Lieven Eeckhout. IEEE Computer Architecture Letters.

Background

Education & teaching

Training across computer science, computer engineering, and architecture research.

  1. Ph.D., Electronics and Information SystemsGhent University
  2. M.S., College of ComputerNational University of Defense Technology
  3. B.S., Computer Science & TechnologyHuazhong University of Science & Technology

Beyond papers

Articles & videos

A collection of insightful and interesting material on architecture, systems, and computing.

Browse collection